Description
The 74279 designed with 4 individual and independent Set-Reset Latches with active-low inputs. Two of the
four latches have a further S input ANDed with the first S input. A Low on any S input while the R input is
HIGH stored within the latch and appear on the corresponding Q output as a HIGH. Whereas the Low on the R input, while the S input is HIGH, will clear the Q output to a low. Meanwhile, the Q output is uncertain due to the simultaneous transition of the R and S inputs from LOW to HIGH. Both inputs are voltage level triggered and do not suffer from the input data transition delay.
The 74C279 designed as a high-speed CMOS QUAD S- R LATCH fabricated in silicon gate C2MOS technology. It offers the same high-speed performance of LSTTL combined with true CMOS low power consumption. Moreover, all inputs are equipped with protection circuits against static discharge and transient excess voltage.
Logic gates are used to make flip flops. A flip-flop circuit can stay in a binary state indefinitely (as long as power is supplied) unless prompted to change states by an input. SET-RESET flip-flops are also known as S-R flip-flops. Two NOR gates and two NAND gates make up the SET-RESET flip-flop. S-R Latch is another name for these flip-flops. The SET [S] and RESET [R] inputs are also included in the design of those flip flops. There are two outputs as well, Q and Q’.
Specifications :
- Quadruple S-R Latch
- High-level output voltage: 3.4V
- Low-level output voltage: 0.2V
- High-level output current: -0.8mA
- Low-level output current: 16mA
- Input clamp voltage: -1.5V
- Propagation delay time max: 27ns
- Supply voltage range: 4.75 to 5.25V
SN74LS279 Datasheet
