82C59 Programmable Interrupt Controller PDIP-28
The MSM82C59A-2 is a programmable interrupt for use in MSM80C85AH and MSM80C86A-10/88A-10 microcomputer systems. Based on CMOS silicon gate technology, this device features an extremely low standby current of 100mA (max.) in chip non-selective status. During interrupt control status, the power consumption is very low with only 5 mA (max.) being required. Internally, the MSM82C59A-2 can control priority interrupts up to 8 levels, and can be expanded up to 64 levels by cascade connection of a number of devices.
Features
- Silicon gate CMOS technology for high speed and low power consumption
- 3 V to 6 V single power supply
- MSM80C85AH system compatibility (MAX5 MHz)
- MSM80C86A-10/88A-10 system compatibility (MAX8 MHz)
- 8-level priority interrupt control
- Interrupt levels expandable up to 64 levels
- Programmable interrupt mode
- Maskable interrupt
- Automatically generated CALL code (85 mode)
- TTL compatible
- 28-pin Plastic DIP
PINOUT
| Pin Symbol | Name | Input/Output | Function |
|---|---|---|---|
| D7–D0 | Bidirectional Data Bus | Input/Output | This 3-state 8-bit bidirectional data bus is used in reading status registers and writing command words through the RD/WR signal from the CPU, and also in reading the CALL instruction code by the INTA signal from the CPU. |
| CS | Chip Select Input | Input | Data transfer with the CPU is enabled by RD/WR when this pin is at low level. The data bus (D0 through D7) is switched to high impedance when this pin is at high level. Note that CS does not affect INTA. |
| RD | Read Input | Input | Data is transferred from the MSM82C59A-2 to the CPU when this pin is at low level. IRR (Interrupt Request Register), ISR (In-Service Register), IMR (Interrupt Mask Register), or a Poll word is selected by OCW3 and A0. |
| WR | Write Input | Input | Commands are transferred from the CPU to the MSM82C59A-2 when this pin is at low level. |
| A0 | Address Input | Input | This pin is used together with the CS, WR, and RD signals to write commands in the command registers, and to select and read status registers. This is normally connected to the least significant bit of the address bus (A0 for MSM80C85A, A1 for MSM80C86A-10/88A-10). |
| CAS0-2 | Cascade Address | Input/Output | These pins are outputs when the MSM82C59A-2 is used as the master, and inputs when used as a slave (in cascade mode). These pins are outputs when in single mode. |
| SP/EN | Slave Program Input / Enable Buffer Output | Input/Output | This dual-function pin is used as an output to enable the data bus buffer in Buffered mode, and as an input for deciding whether the MSM82C59A-2 is to be master (SP/EN = 1) or slave (SP/EN = 0) during Non-buffered mode. |
| INT | Interrupt Output | Output | When an interrupt request is made to the MSM82C59A-2, the INT output is switched to high level, and an INT interrupt is sent to the CPU. |
| INTA | Interrupt Acknowledge Input | Input | When this pin is at low level, the CALL instruction code or the interrupt vector data is enabled onto the data bus. When the CPU acknowledges the INT interrupt, INTA is sent to the MSM82C59A-2. |
| IR0-7 | Request Input | Input | These interrupt request input pins for the MSM82C59A-2 can be set to edge trigger mode or level trigger mode (by ICW1). In edge trigger mode, interrupt requests are executed by the rising edge of the IR input and held until acknowledged by the CPU. In level trigger mode, interrupt requests are executed by high-level IR inputs and held until acknowledged by the CPU. These pins have a pull-up resistor. |
Specifications
| Parameter | Value |
|---|---|
| Function | Programmable Interrupt Controller, 8 levels (cascadeableto64) |
| Compatible CPUs | MSM80C85AH (max 5MHz), MSM80C86A-10/88A-10 (max 8MHz) |
| Supply Voltage | 5V (recommended), operating range 3–6V |
| Absolute Max VCC | −0.5V to +7V |
| Operating Temperature | −40°C to +85°C |
| Package | PDIP-28 |
| Data Bus | 3-state bidirectional D7–D0 for register read/write and CALL code output |
| Interrupt Inputs | IR0–IR7, edge or level triggered (selectable) |
| Control Signals | CS, RD, WR, INTA, A0, SP/EN, CAS0–CAS2 |
| Modes | Fully Nested, Rotate Priority, Special Mask, Polled, AEOI(optional) |
| Typical Power | Low-power CMOS operation (see datasheet for ICC specifics) |
Applications
- Interrupt management for vintage and embedded x80 microcomputer systems and retrocomputing projects.
- Priority and cascade interrupt control in industrial controllers, I/O expanders and multi-processor interfaces.
- Real-time control systems where deterministic interrupt prioritization and masking are required.
- Educational and repair use for legacy PC/embedded boards that employ 82C59A family interrupt controllers.
- Prototype and hobbyist systems requiring programmable interrupt vectors and cascade expansion.
Package Contents
- 1x 82C59 Programmable Interrupt Controller PDIP-28.
Documents
| Datasheet | 82C59 |
Reviews
There are no reviews yet.