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KM4164B-15 DRAM 64K x1 Bit 150ns IC DIP-16
KM4164B-15 NMOS DRAM 150ns, 64Kx1-bit in a 16-pin DIP. Features page mode, single 5V supply, TTL I/O, and requires periodic refresh.
20.00 EGP
Buy NowKM4164B-15 DRAM 64K x1 Bit 150ns IC DIP-16
The KM4164B-15 is a 64Kx1-bit dynamic random-access memory (DRAM) integrated circuit. It stores data as electrical charge within a vast array of 65,536 individual memory cells, each based on a single transistor design. This NMOS (N-type Metal-Oxide-Semiconductor) fabrication allows for high density and a compact chip layout. Data retention in these cells is temporary, necessitating a periodic refresh process every 2 milliseconds to maintain integrity, which can be managed through several dedicated refresh methods.
A key capability of this DRAM is its page mode operation, which significantly speeds up access to multiple bits within the same selected row. It uses a multiplexed address bus, where the same eight pins sequentially receive row and column addresses, controlled by the Row Address Strobe (RAS) and Column Address Strobe (CAS) signals. This efficient pin-out enables it to fit into a standard 16-pin DIP. The device supports versatile write cycles (early, late, and read-modify-write) and features a three-state output buffer controlled primarily by the CAS signal.
The KM4164B-15 is designed for straightforward integration into digital systems, operating from a single +5V power supply with TTL-compatible inputs and output. Its datasheet provides extensive guidance for reliable implementation, emphasizing the critical need for proper board layout to minimize signal skew and the essential use of decoupling capacitors to filter high-frequency noise and prevent data-corrupting voltage droops on the power supply lines.
Features:
- Page Mode capability for high-speed access within a row.
- Single +5V ±10% power supply operation.
- Common I/O capability using early write cycle.
- TTL compatible inputs and output.
- Schmitt Triggers on all input control lines.
- RAS-only and Hidden Refresh capability.
- 128 cycles per 2ms refresh requirement.
- JEDEC standard pinout in 16-pin DIP.
Specifications:
| Category | Parameter | Symbol | Min | Typ | Max | Unit |
|---|---|---|---|---|---|---|
| Speed: | Random Read/Write Cycle Time: | t_{RC} | 260 | ns | ||
| Access Time from RAS: | t_{RAC} | 150 | ns | |||
| Access Time from CAS: | t_{CAC} | 75 | ns | |||
| Power: | Supply Voltage: | V_{CC} | 4.5 | 5.0 | 5.5 | V |
| Operating Current (RAS/CAS Cycling): | I_{CC1} | 45 | mA | |||
| Standby Current: | I_{CC2} | 4 | mA | |||
| Electrical: | Output High Voltage (I_OH = -5mA): | V_{OH} | 2.4 | – | – | V |
| Output Low Voltage (I_OL = 4.2mA): | V_{OL} | – | – | 0.4 | V | |
| Physical: | Package Type: | – | – | – | DIP-16 | – |
Applications:
- Computer Main Memory.
- Peripheral Storage Buffers.
- Memory Expansion Cards.
- Data Buffering in Digital Systems.
Package Contents:
- 1x KM4164B-15 DRAM 64K x1 Bit 150ns IC DIP-16
Datasheet
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