Features:-
- Medium-Speed Operation – tPLH, tPHL = 60 ns (typ.) at VDD = 10 V
- 100% tested for quiescent current at 20 V
- Maximum input current of 1 µA at 18 V over full package-temperature range: 100 nA at 18 V and 25°C
- Noise margin (full package-temperature range) =
- 1 V at VDD = 5 V
- 2 V at VDD = 10 V
- 2.5 V at VDD = 15 V
- Standardized, symmetrical output characteristics
- 5-V, 10-V, and 15-V parametric ratings
Specifications:-
| VCC (Min) (V) | 3 |
| VCC (Max) (V) | 18 |
| Channels (#) | 2 |
| Inputs per channel | 4 |
| Input type | Standard CMOS |
| Output type | Push-Pull |
| Features | Standard Speed (tpd > 50ns) |
| Data rate (Max) (Mbps) | 8 |
| IOL (Max) (mA) | 6.8 |
| IOH (Max) (mA) | -6.8 |
| Operating temperature range (C) | -55 to 125 |
| Package Group | PDIP|14 |
CD4082 Pinout
| Pin No | Pin Name | Description |
|---|---|---|
| 1 | Q0 | output of AND gate 1 |
| 2 | A | input 1 of AND gate 1 |
| 3 | B | input 2 of AND gate 1 |
| 4 | C | input 3 of AND gate 1 |
| 5 | D | input 4 of AND gate 1 |
| 6 | NC | no connection |
| 7 | VSS | source supply |
| 8 | NC | no connection |
| 9 | E | input 1 of AND gate 2 |
| 10 | F | input 2 of AND gate 2 |
| 11 | G | input 3 of AND gate 2 |
| 12 | H | input 4 of AND gate 2 |
| 13 | Q1 | output of AND gate 2 |
| 14 | VDD | Drain supply |
Applications
- Enable and Disable purpose on counter devices
- garden flood-lights
- The chip provides TTL outputs that are needed in some systems.
- security lights
