Description:
This circuit is monolithic J-FET input operational
amplifier incorporating well matched, high voltage
J-FET on the same chip with standard bipolar transistors.
This amplifier features low input bias and offset currents,
low input offset voltage and input offset voltage
drift,coupled with offset adjust which does not degrade
drift or common-mode rejection.
The device is also designed for high slew rate,wide
bandwidth,extremely fast settling time, low voltage and
current noise and a low 1/f noise level.
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